march 2004 copyright ? alliance memory inc. all rights reserved. ? as7c1024b 5v 128k x 8 cmos sram 3/26/04, v 1.2 alliance memory inc p. 1 of 9 features ? industrial and commercial temperatures ? organization: 131,072 words x 8 bits ? high speed - 10/12/15/20 ns address access time - 5/6/7/8 ns output enable access time ? low power consumption: active - 605 mw / max @ 10 ns ? low power consumption: standby - 55 mw / max cmos ? 6t 0.18u cmos technology ? easy memory expansion with ce1 , ce2, oe inputs ? ttl/lvttl-compatible, three-state i/o ? 32-pin jedec standard packages - 300 mil soj - 400 mil soj - 8 20mm tsop 1 - 8 x 13.4mm stsop 1 ? esd protection 2000 volts ? latch-up current 200 ma logic block diagram 512 x 256 x 8 array (1,048,576) sense amp input buffer a10 a11 a12 a13 a14 a15 a16 i/o0 i/o7 oe ce1 we column decoder row decoder control circuit a9 a0 a1 a2 a3 a4 a5 a6 a7 v cc gnd a8 ce2 pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 v cc a15 ce2 we a13 a8 a9 a11 oe a10 ce1 i/o7 i/o6 i/o5 i/o4 i/o3 nc a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 gnd as7c1024b 32-pin soj (300 mil) v cc a15 ce2 we a13 a8 a9 a11 oe a10 ce1 i/o7 i/o6 i/o4 nc a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 gnd i/o5 i/o3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 32 31 30 29 28 27 26 25 24 23 22 21 as7c1024b 20 19 15 16 18 17 32-pin (8 x 20mm) tsop i 32-pin soj (400 mil) 32-pin (8 x 13.4mm) stsop1 selection guide -10 -12 -15 -20 unit maximum address access time 10 12 15 20 ns maximum output enable access time 56 7 8ns maximum operating current 110 100 90 80 ma maximum cmos standby current 10 10 10 10 ma
as7c1024b 3/26/04, v 1.2 alliance memory inc p. 2 of 9 ? functional description the as7c1024b is a high performance cmos 1,048,576-bit static random acce ss memory (sram) device or ganized as 131,072 words x 8 bits. it is designed for memory applica tions where fast data acce ss, low power, and simple interfacing are desired. equal address access and cycle times (t aa , t rc , t wc ) of 10/12/15/20 ns with output enable access times (t oe ) of 5/6/7/8 ns are ideal for high performance applicati ons. active high and low chip enables (ce1 , ce2) permit easy memory expans ion with multiple-bank systems. when ce1 is high or ce2 is low, the devices enter standby m ode. if inputs are still toggling, the devi ce will consume i sb power. if the bus is static, then full standby power is reached (i sb1 ). for example, the as7c1024b is guaranteed not to exceed 55 mw under nominal full standby conditions. a write cycle is accomplished by asserting write enable (we ) and both chip enables (ce1 , ce2). data on the input pins i/o0 through i/o7 is written on the rising edge of we (write cycle 1) or the acti ve-to-inactive edge of ce1 or ce2 (write cycle 2). to avoid bus contention, external devices should drive i/o pins only after outputs ha ve been disabled with output enable (oe ) or write enable (we ). a read cycle is accomplished by asserting output enable (oe ) and both chip enables (ce1 , ce2), with write enable (we ) high. the chips drive i/ o pins with the data word referenced by the input address. when either chip enable is inactive, output enable is inactive, or w rite enable is active, output drivers stay in high-impedance mode. note: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specificat ion is not implied. exposure to absolute maximum rating conditions for extend ed periods may affect reliability. key: x = don?t care, l = low, h = high absolute maximum ratings parameter symbol min max unit voltage on v cc relative to gnd v t1 ?0.50 +7.0 v voltage on any pin relative to gnd v t2 ?0.50 v cc +0.50 v power dissipation p d ?1.0w storage temperature (plastic) t stg ?65 +150 c ambient temperature with v cc applied t bias ?55 +125 c dc current into outputs (low) i out ?20ma truth table ce1 ce2 we oe data mode h x x x high z standby (i sb , i sb1 ) x l x x high z standby (i sb , i sb1 ) l h h h high z output disable (i cc ) lhhl d out read (i cc ) lhlx d in write ( icc )
as7c1024b 3/26/04, v 1.2 alliance memory inc. p. 3 of 9 ? capacitance (f = 1 mhz, t a = 25 c, v cc = nominal) 2 parameter symbol signals test conditions max unit input capacitance c in a, ce1 , ce2, we , oe v in = 0v 5 pf i/o capacitance c i/o i/o v in = v out = 0v 7 pf r ecommended operating conditions v il min = -1.0v for pulse width less than 5ns v ih max = v cc +2.0v for pulse width less than 5ns. d c operating characteristics (over the operating range) 1 parameter symbol min nominal max unit supply voltage v cc 4.5 5.0 5.5 v input voltage v ih 2.2 - v cc + 0.5 v v il ?0.5 ? 0.8 v ambient operating temperature commercial t a 0?70 c industrial t a ?40 ? 85 c parameter sym test conditions -10 -12 -15 -20 unit min max min max min max min max input leakage current |i li |v cc = max, v in = gnd to v cc -1?1?1?1 a output leakage current |i lo | v cc = max, ce1 = v ih or ce2 = v il , v out = gnd to v cc -1?1?1?1 a operating power supply current i cc v cc = max, ce1 v il , ce2 v ih , f = f max , i out = 0 ma - 110 ? 100 ? 90 ? 80 ma standby power supply current i sb v cc = max, ce1 v ih and/or ce2 v il , f = f max -50?45?45?40 ma i sb1 v cc = max, ce1 v cc ?0.2v and/or ce2 0.2v v in 0.2v or v in v cc ? 0.2v, f = 0 -10?10?10?10 output voltage v ol i ol = 8 ma, v cc = min - 0.4 ? 0.4 ? 0.4 ? 0.4 v v oh i oh = ?4 ma, v cc = min 2.4 - 2.4 ? 2.4 ? 2.4 ?
as7c1024b 3/26/04, v 1.2 alliance memory inc p. 4 of 9 ? read cycle (over the operating range) 3,9,12 parameter symbol -10 -12 -15 -20 unit notes min max min max min max min max read cycle time t rc 10-12?15?20?ns address access time t aa -10?12?15?20ns 3 chip enable (ce1 ) access time t ace1 -10?12?15?20ns3, 12 chip enable (ce2) access time t ace2 -10?12?15?20ns3, 12 output enable (oe ) access time t oe -5?6?7?8ns output hold from address change t oh 3-3?3?3?ns 5 ce1 low to output in low z t clz1 3 - 3 ? 3 ? 3 ? ns 4, 5, 12 ce2 high to output in low z t clz2 3 - 3 ? 3 ? 3 ? ns 4, 5, 12 ce1 low to output in high z t chz1 - 4 ? 5 ? 6 ? 7 ns 4, 5, 12 ce2 low to output in high z t chz2 - 4 ? 5 ? 6 ? 7 ns 4, 5, 12 oe low to output in low z t olz 0-0?0?0?ns4, 5 oe high to output in high z t ohz ?4?5?6?7ns4, 5 power up time t pu 0 - 0 ? 0 ? 0 ? ns 4, 5, 12 power down time t pd ?10?12?15?20ns4, 5, 12 key to switching waveforms read waveform 1 (a ddress controlled) 3,6,7,9,12 read waveform 2 (ce1 , ce2, and oe controlled) 3,6,8,9,12 undefined / don?t care falling input rising input a ddress d out data valid t oh t aa t rc supply current ce2 oe d out t oe t olz t ace1 , tace2 t chz1 , t chz2 t clz1 , t clz2 t pu t pd i cc i sb 50% 50% data valid t rc1 ce1 t ohz
as7c1024b 3/26/04, v 1.2 alliance memory inc. p. 5 of 9 ? write waveform 1 (we controlled) 10,11,12 write cycle (over the operating range) 11, 12 parameter symbol -10 -12 -15 -20 unit notes min max min max min max min max write cycle time t wc 10 - 12 ? 15 ? 20 ? ns chip enable (ce1 ) to write end t cw1 8 - 9 ? 10 ? 12 ? ns 12 chip enable (ce2) to write end t cw2 8 - 9 ? 10 ? 12 ? ns 12 address setup to write end t aw 8 - 9 ? 10 ? 12 ? ns address setup time t as 00?0?0?ns12 write pulse width t wp 78?9?12?ns write recovery time t wr 0-0 ? 0?0? ns address hold from end of write t ah 0-0 ? 0?0? ns data valid to write end t dw 56?8?10?ns data hold time t dh 00?0?0?ns4, 5 write enable to output in high z t wz - 5 ? 6 ? 7 ? 8 ns 4, 5 output active from write end t ow 1 - 1 ? 1 ? 2 ? ns 4, 5 t aw t ah t wc address we d out t dh t ow t dw t wz t wp t as data valid d in t wr
as7c1024b 3/26/04, v 1.2 alliance memory inc. p. 6 of 9 ? write waveform 2 (ce1 and ce2 controlled) 10,11,12 ac test conditions notes 1 during v cc power-up, a pull-up resistor to v cc on ce1 is required to meet i sb specification. 2 this parameter is sampled and not 100% tested. 3 for test conditions, see ac test conditions , figures a and b. 4t clz and t chz are specified with cl = 5pf, as in figure c. tr ansition is measured 500 mv from steady-state voltage. 5 this parameter is guaran teed, but not 100% tested. 6we is high for read cycle. 7ce1 and oe are low and ce2 is high for read cycle. 8 address valid prior to or coincident with ce1 transition low. 9 all read cycle timings are referen ced from the last valid address to the first transitioning address. 10 n/a 11 all write cycle timings are referenced from the la st valid address to the first transitioning address. 12 ce1 and ce2 have identical timing. 13 c = 30 pf, except all high z an d low z parameters where c = 5 pf. t aw address ce1 we d out t cw1 , t cw2 t wp t dw t dh t ah t wz t wc t as ce2 data valid d in t wr ? output load: see figure b. ? input pulse level: gnd to 3.5v. see figure a. ? input rise and fall times: 2 ns. see figure a. ? input and output timing reference levels: 1.5v. 168 ? ? ?
as7c1024b 3/26/04, v 1.2 alliance memory inc p. 7 of 9 ? package dimensions seating plane e b e hd d c l a1 a a2 pin 1 pin 32 pin 16 pin 17 pin 1 d e e1 e2 a1 b b a a2 e c 32-pin soj 300 mil 32-pin soj 400 mil min max min max a 0.128 0.145 0.132 0.146 a1 0.025 - 0.025 - a2 0.095 0.105 0.105 0.115 b 0.026 0.032 0.026 0.032 b 0.016 0.020 0.015 0.020 c 0.007 0.010 0.007 0.013 d 0.820 0.830 0.820 0.830 e 0.255 0.275 0.354 0.378 e1 0.295 0.305 0.395 0.405 e2 0.330 0.340 0.435 0.445 e 0.050 bsc 0.050 bsc 32-pin tsop 820 mm min max a ? 1.20 a1 0.05 0.15 a2 0.95 1.05 b 0.17 0.27 c 0.10 0.21 d 18.30 18.50 e 0.50 nominal e 7.90 8.10 hd 19.80 20.20 l 0.50 0.70 0 5
as7c1024b 3/26/04, v 1.2 alliance memory inc p. 8 of 9 ? note: add suffix ?n? to the above part number for lead free parts (ex: as7c1024b-10tcn) ordering codes package \ access time temp 10 ns 12 ns 15 ns 20 ns plastic soj, 300 mil commercial as7c1024b-10tjc as7c1024b-12tjc as7c1024b-15tjc as7c1024b-20tjc industrial ? as7c1024b-12tji as7c1024b-15tji as7c1024b-20tji plastic soj, 400 mil commercial as7c1024b-10jc as7c1024b-12jc as7c1024b-15jc as7c1024b-20jc industrial ? as7c1024b-12ji as7c1024b-15ji as7c1024b-20ji tsop1 820 mm commercial as7c1024b-10tc as7c1024b-12tc as7c1024b-15tc as7c1024b-20tc - stsop1 8 x 13.4mm commercial as7c1024b-10stc as7c1024b-12stc as7c1024b-15stc as7c1024b-20stc industrial ? AS7C1024B-12STI as7c1024b-15sti as7c1024b-20sti part numbering system as7c 1024b ?xx x x x sram prefix device number access time package:t = tsop1 820 mm st = stsop1 8 x 13.4 mm j = soj 400 mil tj = soj 300 mil temperature range c = commercial, 0 c to 70 c i = industrial, -40 c to 85 c n = lead free part
? as7c1024b ? alliance memory, inc. 511 taylor way, san carlos , ca 94 070 tel: 650- 610-6800 fax: 650- 620-9211 www.alliancememory.com copyright ? alliance memory all rights reserved part number: a s7c1024b document version: v. 1.2 ? copyright 2003 alliance memory, inc. all rights reserved. our three-point logo, our name and intelliwatt are trademarks or re gistered trademarks of alliance. all other brand and product names may be the trademarks of their respective companies. alliance reserves the right to make changes to this document and its products at any time without notice. alliance assumes no responsibility for any errors that may appear in this document. the data contained herein represents alliance's best data and/or estimates at the time of issuance. alliance reserves the right to chang e or correct this data at any time, without notice. if the product described herein is under development, significant changes to these specifications are pos sible. the information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intende d to operate as, or provide, any guarantee or warrantee to any user or customer. alliance do es not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warra nties related to the sale and/or use of alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, e xcept as express agreed to in alliance's terms and conditions of sale (which are available from alliance). all sales of alliance products are made exclusivel y according to alliance's terms and conditions of sale. the purchase of products from allia nce does not convey a license under any patent rights, copyrig hts; mask works rights, trademarks, or any other intellectual property rights of allianc e or third parties. alliance do es not authorize its products fo r use as critical components in life-supporting systems where a malfunction or failure may reasonabl y be expected to result in significant injury to the user, and the inclusion of alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to inde mnify alliance against all claims arising from such use.
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